hackfin/cyrite repository overview

This is a cyrite setup with:

• A Jupyter Notebook environment
• ghdl, iverilog, yosys preinstalled

It is supplied for free 'as is'. See https://github.com/hackfin/cyrite.howto⁠ on how to use it to create and verify IP cores via VHDL, Verilog or direct RTL synthesis and CXXRTL from a web browser.