ucirvinelecs/risc062 repository overview

The Recoding Infrastructure for SystemC (RISC) project addresses the advanced parallel simulation of embedded system models with hardware and software components. We focus on Transaction Level Models (TLM 1.0 and TLM-2.0) described in the SystemC language and aim for maximum compliance with the IEEE standard 1666. As simulation host platform, the project targets modern multi- and many-core computer architectures, including the Intel(R) Many Integrated Core (MIC) architecture, such as the Xeon(R) Phi(TM) Coprocessor.

The goal of the project is the efficient analysis and validation of IEEE SystemC design models through high-performance simulation with maximum parallelism for fast and accurate performance analysis and rapid design space exploration. This project encompasses the detailed study and research and development of (1) analysis, compilation and transformation tools for high-level SystemC design models, (2) advanced out-of-order parallel simulation algorithms for the SystemC language, and (3) efficient mapping of parallel threads onto a symmetric many-core platform.

More information can be found here: http://www.cecs.uci.edu/~doemer/risc.html#RISC062⁠

To use this repository use the following commands:

1. sudo docker pull ucirvinelecs/risc062:latest
2. xhost + ( in the terminal before starting the Docker)
3. sudo docker run -it ucirvinelecs/risc062:latest

The above starts a command line version of RISC. Some examples generate graphs and also create visualizable plots. To view these, use one of the following commands instead.

When using a local Linux computer:

sudo docker run -it -v /tmp/.X11-unix:/tmp/.X11-unix -e DISPLAY=unix$DISPLAY ucirvinelecs/risc062:latest

When remotely logged in and using X11 port forwarding:

sudo docker run -it --net=host --env="DISPLAY" --volume="$HOME/.Xauthority:/root/.Xauthority:rw" ucirvinelecs/risc062:latest